Micron M25P40 Serial Flash Embedded Memory
Power-Up/Down and Supply Line Decoupling
Figure 21: Power-Up Timing
V
CC
V
CC,max
PROGRAM, ERASE, and WRITE commands are rejected by the device
Chip selection not allowed
V
CC,min
tVSL
READ access allowed
Device fully
accessible
RESET state
of the
device
V
WI
tPUW
Time
After power-up, the device is in the following state:
• Standby power mode (not the deep power-down mode)
• Write enable latch (WEL) bit is reset
• Write in progress (WIP) bit is reset
• Write lock bit = 0
• Lock down bit = 0
Normal precautions must be taken for supply line decoupling to stabilize the VCC sup-
ply. Each device in a system should have the VCC line decoupled by a suitable capacitor
close to the package pins; generally, this capacitor is of the order of 100 nF.
At power-down, when VCC drops from the operating voltage to below the POR threshold
voltage VWI, all operations are disabled and the device does not respond to any instruc-
tion.
Note:If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,
some data corruption may result.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
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