Micron M25P40 Serial Flash Embedded Memory
Revision History
Revision History
Rev. Y – 8/12
• Updated Command Set to include RELEASE FROM DEEP POWER-DOWN.
• Updated Memory Map to eliminate the 64KB block box.
Rev. X – 04/12
• Updated dimensions for MB package in the Part Number Information Scheme table
in Device Ordering Information.
• In Signal Names table, changed direction column for DQ0 and DQ1 to input and out-
put respectively.
• Changed the Write Disable Command Sequenced graphic.
• Revised Write Status Register topic.
• Revised Power-Up/Down and Supply Line Decoupling topic.
• Revised DFN8 6mm x 5mm package figure.
Rev. W – 03/12
• Updated dimensions for MC package in the Part Number Information Scheme table
in Device Ordering Information.
Rev. V – 02/12
• Corrected error in SO8N package drawing.
• Applied Micron branding.
Rev. U – 09/2011
Rev. 20.0 – 04/2010
Rev. 19.0 – 02/2010
• Corrected package nomenclature.
• Added the following package information: UFDFPN8 (MLP8) 4mm x 3mm and
UFDFPN8 (MLP8) 2mm x 3mm.
Rev. 18.0 – 05/2009
Rev. 17.0 – 02/2009
• Revised cross-references.
• Table 8: Vwi Min (grade 3) = 1V versus 2.1V or (remove one row and grade indication).
• Table: Erase/Program Cycles = 100,000 cycles also for grade 3 (instead of 10,000).
• Table: ICC3 Operating Current (READ) change on test condition section as follows:
OLD: C = 0.1VCC / 0.9VCC at 40 MHz and 75 MHz, Q = open; NEW: C = 0.1VCC / 0.9VCC
at 40 MHz, 50 MHz and 75 MHz, Q = open; OLD: C = 0.1VCC / 0.9.VCC at 25 MHz, Q =
open; NEW: C = 0.1VCC / 0.9VCC at 25 MHz and 33 MHz, Q = open.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
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