Micron M25P40 Serial Flash Embedded Memory
Revision History
• VFQFPN8 package specifications updated.
Rev. 10.0 – 06/2006
Rev. 9.0 – 04/2006
t
• RES1 and tRES2 parameter timings changed for devices produced with the /X process
technology.
• SO8 Narrow package specifications updated.
• Data contained in Table 12 and Table 19 is no longer preliminary.
• Modified Figure: Bus Master and memory devices on the SPI bus.
• 40 MHz frequency condition modified for ICC3 in Table: DC Characteristics (device
grade 3).
• Condition changed for the data retention parameter in Table: Data Retention and En-
durance.
• VWI parameter for device grade 3 added to Table: Power-up Timing and VWI Thresh-
old.
• SO8 package specifications updated.
• /X process added to Table: Ordering Information Scheme.
Rev. 8.0 – 12/2005
Rev. 7.0 – 10/2005
• Note 2 added below Figure 26 and note 3 added below Figure 29.
• RES1 and tRES2 modified in Table 20: AC Characteristics (50 MHz operation, device
grade 6, VCCmin = 2.7V).
t
• Read Identification (RDID) added. Titles of Figure 29 and Table 26 corrected.
• 50 MHz operation added.
• All packages are RoHS-compliant. Blank option removed from under plating technol-
ogy in Table: Ordering Information Scheme.
• MLP package renamed as VFQFPN, silhouette and package mechanical drawing up-
dated.
Rev. 6.0 – 08/2005
Rev. 5.0 – 01/2005
• Updated Page Program commands under heading, "Page Programming, Page Pro-
gram, Instruction Times, Process Technology 110nm."
• Minor text changes.
• Notes 2 and 3 removed from Table: Ordering Information Scheme.
• End timing line of tSHQZ modified in Figure: Output Timing.
Rev. 4.0 – 08/2004
• Device grade information clarified.
• Data-retention measurement temperature corrected.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
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