Micron M25P40 Serial Flash Embedded Memory
Signal Descriptions
Signal Descriptions
Table 2: Signal Descriptions
Signal
Type
Description
DQ1
Output
Serial data: The DQ1 output signal is used to transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock (C).
DQ0
C
Input
Input
Input
Serial data: The DQ0 input signal is used to transfer data serially into the device. It
receives commands, addresses, and the data to be programmed. Values are latched on
the rising edge of the serial clock (C).
Clock: The C input signal provides the timing of the serial interface. Commands, ad-
dresses, or data present at serial data input (DQ0) is latched on the rising edge of the
serial clock (C). Data on DQ1 changes after the falling edge of C.
S#
Chip select: When the S# input signal is HIGH, the device is deselected and DQ1 is at
HIGH impedance. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cy-
cle is in progress, the device will be in the standby power mode (not the DEEP POWER-
DOWN mode). Driving S# LOW enables the device, placing it in the active power
mode. After power-up, a falling edge on S# is required prior to the start of any com-
mand.
HOLD#
W#
Input
Input
Hold: The HOLD# signal is used to pause any serial communications with the device
without deselecting the device. During the hold condition, DQ1 is High-Z. DQ0 and C
are "Don’t Care." To start the hold condition, the device must be selected, with S#
driven LOW.
Write protect: The W# input signal is used to freeze the size of the area of memory
that is protected against program or erase commands as specified by the values in
BP2, BP1, and BP0 bits of the Status Register.
VCC
VSS
Input
Input
Device core power supply: Source voltage.
Ground: Reference for the VCC supply voltage.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
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