Micron M25P40 Serial Flash Embedded Memory
AC Characteristics
Table 24: AC Specifications (75MHz, Device Grade 3 and 6, VCC[min]=2.7V)
Symbol
fC
Alt.
fC
Parameter
Min
D.C.
D.C.
6
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
75
33
–
Unit
MHz
MHz
ns
Notes
Clock frequency for all commands (except READ)
Clock frequency for READ command
fR
–
tCH
tCLH Clock HIGH time
tCLL Clock LOW time
3
tCL
6
–
ns
3, 4
5, 6
5, 6
tCLCH
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ
tCLQV
–
–
Clock rise time (peak to peak)
Clock fall time (peak to peak)
0.1
0.1
5
–
V/ns
V/ns
ns
–
tCSS S# active setup time (relative to C)
S# not active hold time (relative to C)
tDSU Data In setup time
–
5
–
ns
2
–
ns
tDH
–
Data In hold time
5
–
ns
S# active hold time (relative to C)
S# not active setup time (relative to C)
5
–
ns
–
5
–
ns
tCSH S# deselect time
100
–
–
ns
tDIS
tV
Output disable time
8
ns
5
Clock LOW to output valid under 30 pF
Clock LOW to output valid under 10 pF
Output hold time
–
8
ns
–
6
ns
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
tWHSL
tSHWL
tDP
tHO
–
0
–
ns
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# to output LOW-Z
5
–
ns
–
5
–
ns
–
5
–
ns
–
5
–
ns
tLZ
tHZ
–
–
8
ns
5
5
7
7
5
5
HOLD# to output HIGH-Z
–
8
ns
WRITE PROTECT setup time
WRITE PROTECT hold time
20
100
–
–
ns
–
–
ns
–
S# HIGH to DEEP POWER-DOWN mode
3
μs
tRES1
–
S# HIGH to STANDBY without READ ELECTRONIC SIGNA-
TURE
–
30
μs
tRES2
–
S# HIGH to STANDBY with READ ELECTRONIC SIGNATURE
–
–
30
μs
5
1. Applies to entire table: 110nm technology devices are identified by the process identifi-
Notes:
cation digit 4 in the device marking and the process letter B in the part number.
2. Applies to entire table: the AC specification values shown here are allowed only on the
VCC range 2.7V to 3.6V. Maximum frequency in the VCC range 2.3V to 2.7V is 40MHz.
3. The tCH and tCL signal values must be greater than or equal to 1/fC.
4. Typical values are given for TA = 25°C.
5. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, and tRDP signal values are guaranteed by charac-
terization, not 100% tested in production.
6. The tCLCH and tCHCL signals clock rise and fall time values are expressed as a slew-rate.
7. The tWHSL and tSHWL signal values are only applicable as a constraint for a WRITE STATUS
REGISTER command when SRWD bit is set at 1.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
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45
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