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M25P128-VMF6TPB 参数 Datasheet PDF下载

M25P128-VMF6TPB图片预览
型号: M25P128-VMF6TPB
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位,低电压,串行闪存与54 MHz的SPI总线接口 [128-Mbit, low-voltage, serial flash memory with 54-MHz SPI bus interface]
分类和应用: 闪存内存集成电路光电二极管时钟
文件页数/大小: 47 页 / 905 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Instructions  
M25P128  
6.1  
Write enable (WREN)  
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.  
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector  
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.  
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the  
instruction code, and then driving Chip Select (S) High.  
Figure 8.  
Write enable (WREN) instruction sequence  
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction  
High Impedance  
AI02281E  
6.2  
Write disable (WRDI)  
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.  
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the  
instruction code, and then driving Chip Select (S) High.  
The Write Enable Latch (WEL) bit is reset under the following conditions:  
„
Power-up  
„
„
„
„
„
Write Disable (WRDI) instruction completion  
Write Status Register (WRSR) instruction completion  
Page Program (PP) instruction completion  
Sector Erase (SE) instruction completion  
Bulk Erase (BE) instruction completion  
Figure 9.  
Write disable (WRDI) instruction sequence  
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction  
High Impedance  
AI03750D  
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