512Mb, 1Gb, 2Gb: P30-65nm
AC Write Specifications
AC Write Specifications
Table 40: AC Write Specifications
Parameter
Symbol
tPHWL
tELWL
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 12
1, 2
RST# HIGH recovery to WE# LOW
CE# setup to WE# LOW
150
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
WE# write pulse width LOW
Data setup to WE# HIGH
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
tVPWH
tQVVL
50
50
Address setup to WE# HIGH
CE# hold from WE# HIGH
Data hold from WE# HIGH
Address hold from WE# HIGH
WE# pulse width HIGH
50
0
0
0
20
1, 2, 5
VPP setup to WE# HIGH
200
1, 2, 3, 7
VPP hold from status read
WP# hold from status read
WP# setup to WE# HIGH
0
tQVBL
0
200
1, 2, 3, 7
tBHWH
tWHGL
tWHQV
WE# HIGH to OE# LOW
0
1, 2, 9
WE# HIGH to read valid
tAVQV + 35
1, 2, 3, 6, 10
Write to Asynchronous Read Specifications
WE# HIGH to address valid
Write to Synchronous Read Specifications
WE# HIGH to clock valid
tWHAV
0
-
ns
1, 2, 3, 6, 8
tWHCH/L
tWHVH
tWHVL
19
19
7
-
-
-
ns
ns
ns
1, 2, 3, 6, 10
WE# HIGH to ADV# HIGH
WE# HIGH to ADV# LOW
Write Specification with Clock Active
ADV# HIGH to WE# LOW
Clock HIGH to WE# LOW
tVHWL
tCHWL
-
-
20
20
ns
ns
1, 2, 3, 11
1. Write timing characteristics during erase suspend are the same as WRITE-only opera-
tions.
Notes:
2. A WRITE operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width LOW (tWLWH or tELEH) is defined from CE# or WE# LOW (whichever
occurs last) to CE# or WE# HIGH (whichever occurs first). Thus, tWLWH = tELEH = tWLEH
= tELWH.
5. Write pulse width HIGH tWHWL or tEHEL) is defined from CE# or WE# HIGH whichever
occurs first) to CE# or WE# LOW whichever occurs last). Thus, tWHWL = tEHEL = tWHEL
tEHWL).
=
6. tWHVH or tWHCH/L must be met when transitioning from a WRITE cycle to a synchro-
nous BURST read.
7. VPP and WP# should be at a valid level until erase or program success is determined.
8. This specification is only applicable when transitioning from a WRITE cycle to an asyn-
chronous read. See spec tWHCH/L and tWHVH for synchronous read.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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