256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
Signal Descriptions
Signal Descriptions
The signal description table below is a comprehensive list of signals for this device fami-
ly. All signals listed may not be supported on this device. See Signal Assignments for in-
formation specific to this device.
Table 4: Signal Descriptions
Name
Type
Description
A[MAX:0]
Input
Address: Selects the cells in the array to access during READ operations. During WRITE oper-
ations, they control the commands sent to the command interface of the program/erase con-
troller.
CE#
Input
Chip enable: Activates the device, enabling READ and WRITE operations to be performed.
When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z.
OE#
WE#
Input
Input
Input
Output enable: Controls the bus READ operation.
Write enable: Controls the bus WRITE operation of the command interface.
VPP/WP#
VPP/Write Protect: Provides WRITE PROTECT function and VPPH function. These functions
protect the lowest or highest block and enable the device to enter unlock bypass mode, re-
spectively. (Refer to Hardware Protection and Bypass Operations for details.)
BYTE#
RST#
Input
Input
Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is
LOW, the device is in x8 mode; when HIGH, the device is in x16 mode.
Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at
least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after
tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details.
DQ[7:0]
I/O
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation. During
WRITE operations, they represent the commands sent to the command interface of the inter-
nal state machine.
DQ[14:8]
Data I/O: Outputs the data stored at the selected address during a READ operation when
BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE
operations, these bits are not used. When reading the status register, these bits should be ig-
nored.
DQ15/A-1
RY/BY#
I/O
Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as
data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves
as the least significant bit of the address.
Except where stated explicitly otherwise, DQ15 = data I/O (x16 mode); A-1 = address input (x8
mode).
Output Ready busy: Open-drain output that can be used to identify when the device is performing
a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW,
and is High-Z during read mode, auto select mode, and erase suspend mode. After a hard-
ware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET
AC Specifications for more details).
The use of an open-drain output enables the RY/BY# pins from several devices to be connec-
ted to a single pull-up resistor to VCCQ. A low value will then indicate that one (or more) of
the devices is (are) busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to
achieve 0.1V VOL
.
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. B 8/12 EN
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