256Mb and 512Mb (256Mb/256Mb), P30-65nm
Features
List of Figures
Figure 1: 512Mb Easy BGA Block Diagram ...................................................................................................... 10
Figure 2: 512Mb QUAD+ Block Diagram ......................................................................................................... 11
Figure 3: Memory Map – 256Mb and 512Mb ................................................................................................... 12
Figure 4: 56-Pin TSOP – 14mm x 20mm .......................................................................................................... 13
Figure 5: 64-Ball Easy BGA – 10mm x 13mm x 1.2mm ...................................................................................... 14
Figure 6: 88-Ball QUAD+ – 8mm x 11mm x 1.0mm: 256Mb Only ...................................................................... 15
Figure 7: 88-Ball QUAD+ – 8mm x 11mm x 1.2mm: 512Mb Only ...................................................................... 16
Figure 8: 56-Lead TSOP Pinout – 256Mb ......................................................................................................... 17
Figure 9: 64-Ball Easy BGA Ballout – 256Mb, 512Mb ........................................................................................ 18
Figure 10: QUAD+ MCP Ballout ..................................................................................................................... 20
Figure 11: Example VPP Supply Connections ................................................................................................... 38
Figure 12: Block Locking State Diagram .......................................................................................................... 42
Figure 13: First Access Latency Count ............................................................................................................ 47
Figure 14: Example Latency Count Setting Using Code 3 ................................................................................. 48
Figure 15: End of Wordline Timing Diagram ................................................................................................... 48
Figure 16: OTP Register Map .......................................................................................................................... 53
Figure 17: Word Program Procedure ............................................................................................................... 68
Figure 18: Buffer Program Procedure .............................................................................................................. 69
Figure 19: Buffered Enhanced Factory Programming (BEFP) Procedure ........................................................... 70
Figure 20: Block Erase Procedure ................................................................................................................... 71
Figure 21: Program Suspend/Resume Procedure ............................................................................................ 72
Figure 22: Erase Suspend/Resume Procedure ................................................................................................. 73
Figure 23: Block Lock Operations Procedure ................................................................................................... 74
Figure 24: OTP Register Programming Procedure ............................................................................................ 75
Figure 25: Status Register Procedure .............................................................................................................. 76
Figure 26: Reset Operation Waveforms ........................................................................................................... 78
Figure 27: AC Input/Output Reference Timing ................................................................................................ 82
Figure 28: Transient Equivalent Load Circuit .................................................................................................. 82
Figure 29: Clock Input AC Waveform .............................................................................................................. 82
Figure 30: Asynchronous Single-Word Read (ADV# LOW) ................................................................................ 86
Figure 31: Asynchronous Single-Word Read (ADV# Latch) ............................................................................... 86
Figure 32: Asynchronous Page Mode Read ...................................................................................................... 87
Figure 33: Synchronous Single-Word Array or Nonarray Read .......................................................................... 88
Figure 34: Continuous Burst Read with Output Delay ..................................................................................... 89
Figure 35: Synchronous Burst Mode 4-Word Read ........................................................................................... 90
Figure 36: Write to Write Timing .................................................................................................................... 93
Figure 37: Asynchronous Read to Write Timing ............................................................................................... 93
Figure 38: Write to Asynchronous Read Timing ............................................................................................... 94
Figure 39: Synchronous Read to Write Timing ................................................................................................ 95
Figure 40: Write to Synchronous Read Timing ................................................................................................ 96
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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