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JS28F128P30TF75A 参数 Datasheet PDF下载

JS28F128P30TF75A图片预览
型号: JS28F128P30TF75A
PDF下载: 下载PDF文件 查看货源
内容描述: 恒忆Axcell P30-65nm闪存 [Numonyx Axcell P30-65nm Flash Memory]
分类和应用: 闪存
文件页数/大小: 90 页 / 1194 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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P30-65nm SBC  
Figure 35: Buffer Program Flowchart  
Start  
Bus  
Operation  
Command  
Comments  
Data =E8H  
Write to  
Buffer  
Write  
Device  
Supports Buffer  
Writes?  
Addr = Block Address  
Use Single Word  
Programming  
No  
SR. 7 = Valid  
Read  
Addr = Block Address  
(Note 7)  
Yes  
Check SR.7  
1 = Device WSM is Busy  
0 = Device WSM is Ready  
Set Timeout or  
Loop Counter  
Standby  
Yes  
Data =N-1 = Word Count  
N = 0 corresponds to count=1  
Addr = Block Address  
Write  
( Notes1 , 2)  
Clear Status Register  
50h  
Address within Device  
Write  
Data = Write Buffer Data  
( Notes3 , 4)  
Addr =Address within buffer range  
Get Next  
Target Address  
Write  
( Notes5 , 6)  
Data = Write Buffer Data  
Addr = Block Address  
Issue Write to Buffer  
Command E8h  
Block Address  
Program  
Confirm  
Data =D0H  
Addr = Block Address  
Write  
Read  
Status register Data  
CE# and OE# low updates SR  
Addr = Block Address  
Read Status Register  
Block Address  
(note 7)  
Check SR.7  
1 = WSM Ready  
0 = WSM Busy  
No  
Standby  
Notes:  
Timeout  
or Count  
Expired ?  
0 = No  
Is WSM Ready?  
SR. 7=  
Yes  
1. Word count values on DQ0-DQ15 are loaded into the Count  
register. Count ranges for this device are N=0000h to 00FFh.  
.
1 =Yes  
2. The device outputs the Status Register when read.  
Write Word Count  
Block Address  
3. Write Buffer contents will be programmed at the device start  
address or destination flash address .  
Write Buffer Data  
Start Address  
X = X +1  
4. Align the start address on a Write Buffer boundary for  
maximum programming performance (i.e., A8-A1 of the start  
address =0).  
Write Buffer Data  
.
X =0  
Address within buffer range  
5. The device aborts the Buffered Program command if the  
current address is outside the original block address .  
No  
.
6. The Status register indicates an “improper command  
Sequence” if the Buffered Program command is aborted.  
Follow this with a Clear Status Register command .  
No  
Abort Bufferred  
Program?  
X =N?  
Yes  
Yes  
7. The device defaults to output SR data after the Buffered  
Programming Setup Command (E8h) is issued . CE# or OE#  
must be be toggled to update Status Register. Don’t issue the  
Read SR command (70h), which would be interpreted by the  
internal state machine as Buffer Word Count.  
Write Confirm D0h  
Block Address  
Write to another  
Block Address  
Buffered Program  
Aborted  
8. Full status check can be done after all erase and write  
sequences complete . Write FFh after the last operation to  
reset the device to read array mode.  
Read Status Register  
No  
Suspend  
Program  
Loop  
Yes  
Suspend  
Program  
0
SR. 7=?  
1
Full Status  
Check if Desired  
Yes  
Another Buffered  
Programming?  
No  
Program Complete  
Datasheet  
76  
Apr 2010  
Order Number: 208033-02  
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