32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
General Description
General Description
The M29EW is an asynchronous, parallel NOR Flash memory device manufactured on
65nm single-bit cell (SBC) technology. READ, ERASE, and PROGRAM operations are
performed using a single low-voltage supply. Upon power-up, the device defaults to
read array mode.
The main memory array is divided into uniform blocks that can be erased independent-
ly so that valid data can be preserved while old data is purged. PROGRAM and ERASE
commands are written to the command interface of the memory. An on-chip program/
erase controller simplifies the process of programming or erasing the memory by taking
care of all special operations required to update the memory contents. The end of a
PROGRAM or ERASE operation can be detected and any error condition can be identi-
fied. The command set required to control the device is consistent with JEDEC stand-
ards.
CE#, OE#, and WE# control the bus operation of the device and enable a simple con-
nection to most microprocessors, often without additional logic.
The M29EW supports asynchronous random read and page read from all blocks of the
array. It also features an internal program buffer that improves throughput by program-
ming 256 words via one command sequence. The device contains a 128-word extended
memory block which overlaps addresses with array block 0. The user can program this
additional space and then protect it to permanently secure the contents. The device al-
so features different levels of hardware and software protection to secure blocks from
unwanted modification.
Figure 1: Logic Diagram
VCC
VCCQ
VPP/WP#
15
A[MAX:0]
DQ[14:0]
DQ15/A-1
RY/BY#
WE#
CE#
OE#
RST#
BYTE#
VSS
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
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