32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 8
Figure 2: 56-Pin TSOP (Top View) .................................................................................................................... 9
Figure 3: 48-Pin TSOP (Top View) .................................................................................................................. 10
Figure 4: 48-Ball BGA (Top and Bottom Views) ............................................................................................... 11
Figure 5: 64-Ball Fortified BGA (Top and Bottom Views) .................................................................................. 12
Figure 6: Data Polling Flowchart .................................................................................................................... 24
Figure 7: Toggle Bit Flowchart ........................................................................................................................ 25
Figure 8: Status Register Polling Flowchart ..................................................................................................... 26
Figure 9: Lock Register Program Flowchart ..................................................................................................... 28
Figure 10: Boundary Condition of Program Buffer Size .................................................................................... 39
Figure 11: WRITE TO BUFFER PROGRAM Flowchart ...................................................................................... 40
Figure 12: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 52
Figure 13: Software Protection Scheme .......................................................................................................... 57
Figure 14: Power-Up Timing .......................................................................................................................... 64
Figure 15: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 65
Figure 16: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 65
Figure 17: AC Measurement Load Circuit ....................................................................................................... 67
Figure 18: AC Measurement I/O Waveform ..................................................................................................... 67
Figure 19: Random Read AC Timing (8-Bit Mode) ........................................................................................... 71
Figure 20: Random Read AC Timing (16-Bit Mode) ......................................................................................... 71
Figure 21: BYTE# Transition Read AC Timing .................................................................................................. 72
Figure 22: Page Read AC Timing (16-Bit Mode) ............................................................................................... 72
Figure 23: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 74
Figure 24: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 75
Figure 25: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 77
Figure 26: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 78
Figure 27: Chip/Block Erase AC Timing (8-Bit Mode) ...................................................................................... 79
Figure 28: Accelerated Program AC Timing ..................................................................................................... 80
Figure 29: Data Polling AC Timing .................................................................................................................. 80
Figure 30: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 81
Figure 31: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 83
Figure 32: 48-Pin TSOP – 12mm x 20mm ........................................................................................................ 84
Figure 33: 48-Ball BGA – 6mm x 8mm ............................................................................................................. 85
Figure 34: 64-Ball Fortified BGA – 11mm x 13mm ........................................................................................... 86
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
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