512Mb, 1Gb, 2Gb: P33-65nm
AC Read Specifications
Figure 32: Synchronous Burst Mode 4-Word Read
tAVCH
Latency count
tVLCH tCHAX
CLK
tAVQV
tAVVH
A
A
tVHAX
tVHVL
tELVH
ADV#
tELCH
tEHQZ
tGHQZ
tELQV
CE#
OE#
tGLTV
tCHTV
tCHQV
tGHTZ
WAIT
DQ
tCHQV
tCHQX
tGLQV
tGLQX
tOH
Q0
Q1
Q2
Q3
1. WAIT is driven per OE# assertion during synchronous array or nonarray read. WAIT as-
serted during initial latency and deasserted during valid data (RCR10 = 0, WAIT asserted
LOW).
Note:
PDF: 09005aef845667b8
p33_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. C 12/13 EN
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