512Mb, 1Gb, 2Gb: P33-65nm
Common Flash Interface
Table 29: Partition Region 1 Information (Continued)
Hex Offset
P = 10Ah
Description
Address
Bottom/Top
Optional Flash features and commands
Length
Bottom/Top
(P+30)h
(P+31)h
Partition 1 (erase block type 1):
Minimum block erase cycles x 1000
2
13A:
13B:
(P+32)h
(P+33)h
Partition 1 (erase block type 1) bits per cell; internal ECC:
Bits 0 - 3 = bits per cell in erase region
Bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
Bit 5 - 7 = reserved for future use
1
1
13C:
Partition 1 (erase block type 1) page mode and synchronous
mode capabilities:
13D:
Bits 0 = page-mode host reads permitted (1=yes, 0=no)
Bit 1 = synchronous host reads permitted (1=yes, 0=no)
Bit 2 = synchronous host writes permitted (1=yes, 0=no)
Bit 3 - 7 = reserved for future use
(P+34)h
(P+35)h
(P+36)h
(P+37)h
(P+38)h
(P+39)h
Partition 1 (erase block type 1) programming region information:
Bits 0 - 7 = x, 2x: programming region aligned size (bytes)
Bit 8-14 = reserved for future use
Bit 15 = legacy flash operation; ignore 0:7
Bit 16 - 23 = y: control mode valid size (bytes)
Bit 24 - 31 = reserved for future use
6
13E:
13F:
140:
141:
142:
143:
Bit 32 - 39 = z: control mode invalid size (bytes)
Bit 40 - 46 = reserved for future use
Bit 47 = legacy flash operation (ignore 23:16 and 39:32)
(P+3A)h
(P+3B)h
(P+3C)h
(P+3D)h
Partition 1 erase block type 2 information:
Bits 0-15 = y, y+1 = Number of identical-size erase blocks in a par-
tition.
Bits 16 - 31 = z, where region erase block(s) size is z x 256 bytes.
(bottom parameter device only)
4
144:
145:
146:
147:
(P+3E)h
(P+3F)h
Partition 1 (erase block type 2)
Minimum block erase cycles x 1000
2
1
148:
149:
14A:
(P+40)h
Partition 1 (erase block type 2) bits per cell, internal EDAC:
Bits 0 - 3 = bits per cell in erase region
Bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
Bits 5 - 7 = reserved for future use
(P+41)h
Partition 1 (erase block type 2) page mode and synchronous
mode capabilities:
1
14B:
Bit 0 = page-mode host reads permitted (1=yes, 0=no)
Bit 1 = synchronous host reads permitted (1=yes, 0=no)
Bit 2 = synchronous host writes permitted (1=yes, 0=no)
Bits 3-7 = reserved for future use
PDF: 09005aef845667b8
p33_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. C 12/13 EN
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