32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Signal Descriptions
Signal Descriptions
The signal description table below is a comprehensive list of signals for this device fami-
ly. All signals listed may not be supported on this device. See Signal Assignments for in-
formation specific to this device.
Table 4: Signal Descriptions
Name
Type
Description
A[MAX:0]
Input
Address: Selects the cells in the array to access during READ operations. During WRITE oper-
ations, they control the commands sent to the command interface of the program/erase con-
troller.
CE#
Input
Chip enable: Activates the device, enabling READ and WRITE operations to be performed.
When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z.
OE#
WE#
Input
Input
Input
Output enable: Controls the bus READ operation.
Write enable: Controls the bus WRITE operation of the command interface.
VPP/WP#
VPP/Write Protect: Provides WRITE PROTECT function and VPPH function. These functions
protect the lowest or highest block or top two blocks or bottom two blocks, enable the de-
vice to enter unlock bypass mode and accelerate program speed, respectively. (Refer to Hard-
ware Protection, Bypass Operations, and Program Operations for details.)
A 0.1μF capacitor should be connected between VPP/WP# and VSS to decouple the current
surges from the power supply when VPPH is applied. The PCB track widths must be sufficient
to carry the currents required during PROGRAM and ERASE operation when VPPH is applied
(see DC Characteristics).
BYTE#
RST#
Input
Input
Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is
LOW, the device is in x8 mode; when HIGH, the device is in x16 mode.
Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at
least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after
tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details.
DQ[7:0]
I/O
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation. During
WRITE operations, they represent the commands sent to the command interface of the inter-
nal state machine.
DQ[14:8]
Data I/O: Outputs the data stored at the selected address during a READ operation when
BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE
operations, these bits are not used. When reading the status register, these bits should be ig-
nored.
DQ15/A-1
I/O
Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as
data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves
as the least significant bit of the address.
Except where stated explicitly otherwise, DQ15 = data I/O (x16 mode); A-1 = address input (x8
mode).
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
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