32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Power-Up and Reset Characteristics
Power-Up and Reset Characteristics
Table 29: Power-Up Specifications
Symbol
Parameter
Legacy
JEDEC
Min
0
Unit
µs
Notes
VCC HIGH to VCCQ HIGH
–
tVCHVCQH
tVCHPH
tVCQHPH
tPHEL
1
2
2
VCC HIGH to rising edge of RST#
VCCQ HIGH to rising edge of RST#
RST# HIGH to chip enable LOW
RST# HIGH to write enable LOW
tVCS
tVIOS
tRH
60
0
µs
µs
50
150
ns
–
tPHWL
ns
1. VCC and VCCQ ramps must be synchronized during power-up.
Notes:
2. If RST# is not stable for tVCS or tVIOS, the device will not allow any READ or WRITE oper-
ations, and a hardware reset is required.
Figure 14: Power-Up Timing
tVCHVCQH
VCC
VCCQ
tRH
CE#
tVIOS
RST#
tVCS
WE#
tPHWL
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