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JR28F032M29EWXX 参数 Datasheet PDF下载

JR28F032M29EWXX图片预览
型号: JR28F032M29EWXX
PDF下载: 下载PDF文件 查看货源
内容描述: [Parallel NOR Flash Embedded Memory]
分类和应用:
文件页数/大小: 87 页 / 1118 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash  
Erase Operations  
When the device exits auto select mode, the device reverts to program suspend mode  
and is ready for another valid operation.  
The PROGRAM SUSPEND operation is aborted by performing a device reset or power-  
down. In this case, data integrity cannot be ensured, and it is recommended that the  
words or bytes that were aborted be reprogrammed.  
PROGRAM RESUME Command  
The PROGRAM RESUME (30h) command must be issued to exit a program suspend  
mode and resume a PROGRAM operation. The controller can use DQ7 or DQ6 status  
bits to determine the status of the PROGRAM operation. After a PROGRAM RESUME  
command is issued, subsequent PROGRAM RESUME commands are ignored. Another  
PROGRAM SUSPEND command can be issued after the device has resumed program-  
ming.  
Erase Operations  
CHIP ERASE Command  
The CHIP ERASE (80/10h) command erases the entire chip. Six bus WRITE operations  
are required to issue the command and start the program/erase controller.  
Protected blocks are not erased. If all blocks are protected, the CHIP ERASE operation  
appears to start, but will terminate within approximately100μs, leaving the data un-  
changed. No error is reported when protected blocks are not erased.  
During the CHIP ERASE operation, the device ignores all other commands, including  
ERASE SUSPEND. It is not possible to abort the operation. All bus READ operations dur-  
ing CHIP ERASE output the status register on the data I/Os. See the Status Register sec-  
tion for more details.  
After the CHIP ERASE operation completes, the device returns to read mode, unless an  
error has occurred. If an error occurs, the device will continue to output the status regis-  
ter. A READ/RESET command must be issued to reset the error condition and return to  
read mode.  
The CHIP ERASE command sets all of the bits in unprotected blocks of the device to 1.  
All previous data is lost.  
The operation is aborted by performing a reset or by powering-down the device. In this  
case, data integrity cannot be ensured, and it is recommended that the entire chip be  
erased again.  
UNLOCK BYPASS CHIP ERASE Command  
When the device is in unlock bypass mode, the UNLOCK BYPASS CHIP ERASE (80/10h)  
command can be used to erase all memory blocks at one time. The command requires  
only two bus WRITE operations instead of six using the standard CHIP ERASE com-  
mand. The final bus WRITE operation starts the program/erase controller.  
The UNLOCK BYPASS CHIP ERASE command behaves the same way as the CHIP  
ERASE command: the operation cannot be aborted, and a bus READ operation to the  
memory outputs the status register.  
PDF: 09005aef84dc44a7  
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2012 Micron Technology, Inc. All rights reserved.  
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