32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
6. When DQ5 is set to 1, a READ/RESET command must be issued before any subsequent
command.
Table 14: Operations and Corresponding Bit Settings
Note 1 applies to entire table
Operation
PROGRAM
Address
DQ7
DQ6
DQ5
DQ3
DQ2
–
DQ1
RY/BY# Notes
Any address
Any address
DQ7#
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
0
0
0
0
0
0
0
–
–
1
0
0
1
1
0
0
–
–
–
–
–
0
2
BLANK CHECK
CHIP ERASE
1
0
0
0
0
0
–
0
Any address
Toggle
Toggle
No toggle
Toggle
No toggle
0
BLOCK ERASE
before time-out
Erasing block
Non-erasing block
Erasing block
Non-erasing block
0
0
BLOCK ERASE
0
0
PROGRAM
SUSPEND
Programming
block
Invalid operation
High-Z
Nonprogramming
block
Outputs memory array data as if in read mode
High-Z
ERASE
SUSPEND
Erasing blk
Non-erasing blk
Erasing block
1
No Toggle
0
–
Toggle
–
High-Z
High-Z
0
Outputs memory array data as if in read mode
PROGRAM during
ERASE SUSPEND
DQ7#
Toggle
Toggle
Toggle
0
0
0
–
–
–
Toggle
No Toggle
–
–
–
1
2
2
Non-erasing block DQ7#
0
BUFFERED
Any address
DQ7#
High-Z
PROGRAM ABORT
PROGRAM Error
ERASE Error
Any address
Erase success block
Erase fail block
Any address
DQ7#
Toggle
Toggle
Toggle
Toggle
1
1
1
1
–
1
1
1
–
–
–
–
–
High-Z
High-Z
High-Z
High-Z
2
0
0
1
No toggle
Toggle
Toggle
BLANK CHECK Er-
ror
1. Unspecified data bits should be ignored.
2. DQ7# for buffer program is related to the last address location loaded.
Notes:
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
23
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