CHARGE PUMP DC-TO-DC
VOLTAGE CONVERTER
TC7660
The four switches in Figure 2 are MOS power switches;
S
1
is a P-channel device, and S
2
, S
3
and S
4
are N-channel
devices. The main difficulty with this approach is that in
integrating the switches, the substrates of S
3
and S
4
must
always remain reverse-biased with respect to their sources,
but not so much as to degrade their ON resistances. In
addition, at circuit start-up, and under output short circuit
conditions (V
OUT
= V
+
), the output voltage must be sensed
and the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and probable
device latch-up.
This problem is eliminated in the TC7660 by a logic
network which senses the output voltage (V
OUT
) together
with the level translators, and switches the substrates of S
3
and S
4
to the correct level to maintain necessary reverse
bias.
The voltage regulator portion of the TC7660 is an
integral part of the anti-latch-up circuitry. Its inherent voltage
drop can, however, degrade operation at low voltages. To
improve low-voltage operation, the LV pin should be
connected to GND, disabling the regulator. For supply
voltages greater than 3.5V, the LV terminal must be left
open to ensure latch-up-proof operation and prevent device
damage.
IS
1
2
C1
10µF
+
3
4
8
7
IL
V+
(+5V)
TC7660
6
5
COSC
*
RL
VO
C2
10µF
+
NOTES:
* For large values of COSC (>1000pF), the values
of C1 and C2 should be increased to 100µF.
Figure 1. TC7660 Test Circuit
Detailed Description
The TC7660 contains all the necessary circuitry to
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10
µF
polar-
ized electrolytic capacitors. Operation is best understood by
considering Figure 2, which shows an idealized voltage
inverter. Capacitor C
1
is charged to a voltage, V
+
, for the half
cycle when switches S
1
and S
3
are closed. (Note: Switches
S
2
and S
4
are open during this half cycle.) During the second
half cycle of operation, switches S
2
and S
4
are closed, with
S
1
and S
3
open, thereby shifting capacitor C
1
negatively by
V
+
volts. Charge is then transferred from C
1
to C
2
, such that
the voltage on C
2
is exactly V
+
, assuming ideal switches and
no load on C
2
.
Theoretical Power Efficiency
Considerations
In theory, a capacitive charge pump can approach
100% efficiency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
V+
S1
S2
GND
S3
S4
C2
VOUT
= – VIN
Figure 2. Idealized Charge Pump Inverter
© 2001 Microchip Technology Inc.
DS21465A
5
TC7660-7 9/30/96
MICROCHIP [ MICROCHIP TECHNOLOGY ]
