TC7129
4.11
Successive Integration
4.12
Digital Auto-Zeroing
The successive integration technique picks up where
dual slope conversion ends. The over shoot voltage
shown in Figure 4-9, called the "integrator residue volt-
age," is measured to obtain a correction to the initial
count. Figure 4-10 shows the cycles in a successive
integration measurement.
The waveform shown is for a negative input signal. The
sequence of events during the measurement cycle is
shown in Table 4-1.
To eliminate the effect of amplifier offset errors, the
TC7129 uses a digital auto-zeroing technique. After the
input voltage is measured as described above, the
measurement is repeated with the inputs shorted inter-
nally. The reading with inputs shorted is a measure-
ment of the internal errors and is subtracted from the
previous reading to obtain a corrected measurement.
Digital auto-zeroing eliminates the need for an external
auto-zeroing capacitor used in other ADCs.
TABLE 4-1:
MEASUREMENT CYCLE
SEQUENCE
Description
4.13
Inside the TC7129
Figure 4-11 shows a simplified block diagram of the
TC7129.
Phase
INT
1
DE
1
Input signal is integrated for fixed time (1000 clock
cycles on 2V scale, 10,000 on 200 mV).
Integrator voltage is ramped to zero. Counter
counts up until zero crossing to produce reading
accurate to 3-1/2 digits. Residue represents an
over shoot of the actual input voltage.
Residue voltage is amplified 10 times and inverted.
Integrator voltage is ramped to zero. Counter
counts down until zero crossing to correct reading
to 4-1/2 digits. Residue represents an under shoot
of the actual input voltage.
Residue voltage is amplified 10 times and inverted.
Integrator voltage is ramped to zero. Counter
counts up until zero crossing to correct reading to
5-1/2 digits. Residue is discarded.
REST Rest; circuit settles.
X10
DE
2
REST Rest; circuit settles.
X10
DE
3
2002 Microchip Technology Inc.
DS21459B-page 13
©
MICROCHIP [ MICROCHIP TECHNOLOGY ]
