PIC32MX1XX/2XX
4.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source.For
detailed information, refer to
Section 3.
“Memory Organization”
(DS61115) in
the
“PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
4.1
PIC32MX1XX/2XX Memory Layout
PIC32MX1XX/2XX microcontrollers implement two
address schemes: virtual and physical. All hardware
resources, such as program memory, data memory
and peripherals, are located at their respective physical
addresses. Virtual addresses are exclusively used by
the CPU to fetch and execute instructions as well as
access peripherals. Physical addresses are used by
bus master peripherals, such as DMA and the Flash
controller, that access memory independently of the
CPU.
The memory maps for the PIC32MX1XX/2XX devices
are illustrated in
and
PIC32MX1XX/2XX microcontrollers provide 4 GB of
unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX1XX/2XX
devices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
(KSEG0/KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
©
2011-2012 Microchip Technology Inc.
Preliminary
DS61168D-page 37
MICROCHIP [ MICROCHIP TECHNOLOGY ]
