PIC18F97J60 FAMILY
Pin Diagrams (Continued)
100-Pin TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RH1/A17
RH0/A16
RE2/AD10/CS/P2B
RE3/AD11/P3C
(2)
RE4/AD12/P3B
(2)
RE5/AD13/P1C
(2)
RE6/AD14/P1B
(2)
RE7/AD15/ECCP2
(1)
/P2A
(1)
RD0/AD0/PSP0
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4/SDO2
RD5/AD5/PSP5/SDI2/SDA2
V
DD
V
SS
RD6/AD6/PSP6/SCK2/SCL2
RD7/AD7/PSP7/SS2
V
SSPLL
V
DDPLL
RBIAS
V
SSTX
TPOUT+
TPOUT-
V
DDTX
RH2/A18
RH3/A19
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3/ECCP2
(1)
/P2A
(1)
NC
RG6
RG5
RF0/AN5
MCLR
RG4/CCP5/P1D
V
SS
V
DDCORE
/V
CAP
V
DD
RF7/SS1
RF6/AN11
RF5/AN10/CV
REF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15/P1B
(2)
RH6/AN14/P1C
(2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC18F96J60
PIC18F96J65
PIC18F97J60
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DDRX
TPIN+
TPIN-
V
SSRX
RG0/ECCP3/P3A
RG1/TX2/CK2
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
RJ2/WRL
V
SS
OSC2/CLKO
OSC1/CLKI
V
DD
RJ3/WRH
V
SS
V
DD
RJ6/LB
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RG2/RX2/DT2
RG3/CCP4/P3D
RH5/AN13/P3B
(2)
RH4/AN12/P3C
(2)
RF1/AN6/C2OUT
ENVREG
AV
DD
AV
SS
RA3/AN3/V
REF
+
RA2/AN2/V
REF
-
RA1/LEDB/AN1
RA0/LEDA/AN0
V
SS
V
DD
RG7
RJ7/UB
V
SS
RA5/AN4
RA4/T0CKI
Note 1:
2:
The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings.
P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.
©
2009 Microchip Technology Inc.
RC1/T1OSI/ECCP2
(1)
/P2A
(1)
RC0/T1OSO/T13CKI
RC6/TX1/CK1
RC7/RX1/DT1
RJ4/BA0
RJ5/CE
RJ0/ALE
RJ1/OE
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DS39762E-page 7
MICROCHIP [ MICROCHIP TECHNOLOGY ]
