PIC18F45J10 FAMILY
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
CMIE
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
BCL1IE
CCP2IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit
1= Enabled
0= Disabled
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1= Enabled
0= Disabled
bit 2-1
bit 0
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1= Enabled
0= Disabled
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
SSP2IE
bit 7
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
BCL2IE
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1= Enabled
0= Disabled
bit 6
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1= Enabled
0= Disabled
bit 5-0
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
DS39682E-page 91