PIC18F45J10 FAMILY
21.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F45J10
FAMILY DEVICES
21.0 SPECIAL FEATURES OF THE
CPU
PIC18F45J10 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
Unlike most PIC18 microcontrollers, devices of the
PIC18F45J10 family do not use persistent memory
registers to store configuration information. The config-
uration bytes are implemented as volatile memory
which means that configuration data must be
programmed each time the device is powered up.
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Configuration data is stored in the four words at the top
of the on-chip program memory space, known as the
Flash Configuration Words. It is stored in program
memory in the same order shown in Table 21-1, with
CONFIG1L at the lowest address and CONFIG3H at
the highest. The data is automatically loaded in the
proper Configuration registers during device power-up.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data; this is
to make certain that program code is not stored in this
address when the code is compiled.
• In-Circuit Serial Programming™ (ICSP™)
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 3.0
“Oscillator Configurations”.
The volatile memory cells used for the Configuration
bits always reset to ‘1’ on Power-on Resets. For all
other type of Reset events, the previously programmed
values are maintained and used without reloading from
program memory.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F45J10 family of
devices have a configurable Watchdog Timer which is
controlled in software.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires a device Reset.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
21.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h. A complete list
is shown in Table 21-1. A detailed explanation of the
various bit functions is provided in Register 21-1
through Register 21-8.
© 2009 Microchip Technology Inc.
DS39682E-page 235
MICROCHIP [ MICROCHIP ]
