PIC18F4520-I/ML 参数 Datasheet PDF下载

型号：	PIC18F4520-I/ML
PDF下载：	下载PDF文件查看货源
内容描述：	28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用：	闪存微控制器和处理器外围集成电路时钟
文件页数/大小：	412 页 / 6898 K
品牌：	MICROCHIP [ MICROCHIP ]

PIC18F2420/2520/4420/4520

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

ADRESH

ADRESL

ADCON0

ADCON1

ADCON2

CCPR1H

CCPR1L

2420

2520

4420

4520

xxxx xxxx

--00 0000

uuuu uuuu

--00 0000

uuuu uuuu

--uu uuuu

u-uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu uuuu

uuuu u-uu

uuuu uuuu

uuuu uu--

uuuu uuuu

0000 0000

uu-0 u000

(6)

--00 0qqq

0-00 0000

xxxx xxxx

0000 0000

--00 0000

xxxx xxxx

--00 0000

0100 0-00

0000 0000

0000 00--

0000 0000

0000 0111

xxxx xxxx

0000 0000

0000 0010

0000 000x

0000 0000

xx-0 x000

0-00 0000

uuuu uuuu

0000 0000

--00 0000

uuuu uuuu

--00 0000

0100 0-00

0000 0000

0000 00--

0000 0000

0000 0111

uuuu uuuu

0000 0000

0000 0010

0000 000x

0000 0000

uu-0 u000

CCP1CON

CCPR2H

CCPR2L

CCP2CON

BAUDCON

PWM1CON

ECCP1AS

CVRCON

CMCON

TMR3H

TMR3L

T3CON

SPBRGH

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADR

EEDATA

EECON2

EECON1

Legend:

u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as

PORTA pins, they are disabled and read ‘0’.

6: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When

PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.

DS39631E-page 51

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