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PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
SLEEP  
Enter Sleep mode  
SUBFWB  
Subtract f from W with Borrow  
Syntax:  
SLEEP  
None  
Syntax:  
SUBFWB f {,d {,a}}  
Operands:  
Operation:  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
00h WDT,  
0WDT postscaler,  
1TO,  
Operation:  
(W) – (f) – (C) dest  
0PD  
Status Affected:  
Encoding:  
N, OV, C, DC, Z  
Status Affected:  
Encoding:  
TO, PD  
0101  
01da  
ffff  
ffff  
0000  
0000  
0000  
0011  
Description:  
Subtract register ‘f’ and Carry flag  
(borrow) from W (2’s complement  
method). If ‘d’ is ‘0’, the result is stored  
in W. If ‘d’ is ‘1’, the result is stored in  
register ‘f’ (default).  
Description:  
The Power-Down status bit (PD) is  
cleared. The Time-out status bit (TO)  
is set. Watchdog Timer and its post-  
scaler are cleared.  
The processor is put into Sleep mode  
with the oscillator stopped.  
If ‘a’ is ‘0’, the Access Bank is  
selected. If ‘a’ is ‘1’, the BSR is used  
to select the GPR bank (default).  
If ‘a’ is ‘0’ and the extended instruction  
set is enabled, this instruction  
operates in Indexed Literal Offset  
Addressing mode whenever  
f 95 (5Fh). See Section 24.2.3  
“Byte-Oriented and Bit-Oriented  
Instructions in Indexed Literal Offset  
Mode” for details.  
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Decode  
No  
operation  
Process  
Data  
Go to  
Sleep  
Example:  
SLEEP  
Words:  
Cycles:  
1
1
Before Instruction  
TO  
PD  
=
=
?
?
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
After Instruction  
Decode  
Read  
register ‘f’  
Process  
Data  
Write to  
destination  
TO  
PD  
=
=
1 †  
0
Example 1:  
SUBFWB  
REG, 1, 0  
If WDT causes wake-up, this bit is cleared.  
Before Instruction  
REG  
W
C
=
=
=
3
2
1
After Instruction  
REG  
W
C
=
FF  
2
=
=
=
=
0
Z
0
1
N
; result is negative  
Example 2:  
SUBFWB  
REG, 0, 0  
Before Instruction  
REG  
W
=
=
=
2
5
1
C
After Instruction  
REG  
W
C
=
2
3
1
0
=
=
=
=
Z
N
0
; result is positive  
Example 3:  
Before Instruction  
SUBFWB  
REG, 1, 0  
REG  
W
=
=
=
1
2
0
C
After Instruction  
REG  
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero  
N
DS39631E-page 302  
© 2008 Microchip Technology Inc.  
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