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PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)  
R/P-1  
U-0  
U-0  
U-0  
U-0  
R/P-0  
R/P-1  
R/P-1  
MCLRE  
LPT1OSC  
PBADEN  
CCP2MX  
bit 7  
bit 0  
Legend:  
R = Readable bit  
P = Programmable bit  
U = Unimplemented bit, read as ‘0’  
-n = Value when device is unprogrammed  
u = Unchanged from programmed state  
bit 7  
MCLRE: MCLR Pin Enable bit  
1= MCLR pin enabled; RE3 input pin disabled  
0= RE3 input pin enabled; MCLR disabled  
bit 6-3  
bit 2  
Unimplemented: Read as ‘0’  
LPT1OSC: Low-Power Timer1 Oscillator Enable bit  
1= Timer1 configured for low-power operation  
0= Timer1 configured for higher power operation  
bit 1  
bit 0  
PBADEN: PORTB A/D Enable bit  
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)  
1= PORTB<4:0> pins are configured as analog input channels on Reset  
0= PORTB<4:0> pins are configured as digital I/O on Reset  
CCP2MX: CCP2 MUX bit  
1= CCP2 input/output is multiplexed with RC1  
0= CCP2 input/output is multiplexed with RB3  
REGISTER 23-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)  
R/P-1  
R/P-0  
U-0  
U-0  
U-0  
R/P-1  
LVP  
U-0  
R/P-1  
DEBUG  
XINST  
STVREN  
bit 7  
bit 0  
Legend:  
R = Readable bit  
P = Programmable bit  
U = Unimplemented bit, read as ‘0’  
-n = Value when device is unprogrammed  
u = Unchanged from programmed state  
bit 7  
bit 6  
DEBUG: Background Debugger Enable bit  
1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins  
0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug  
XINST: Extended Instruction Set Enable bit  
1= Instruction set extension and Indexed Addressing mode enabled  
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)  
bit 5-3  
bit 2  
Unimplemented: Read as ‘0’  
LVP: Single-Supply ICSP™ Enable bit  
1= Single-Supply ICSP enabled  
0= Single-Supply ICSP disabled  
bit 1  
bit 0  
Unimplemented: Read as ‘0’  
STVREN: Stack Full/Underflow Reset Enable bit  
1= Stack full/underflow will cause Reset  
0= Stack full/underflow will not cause Reset  
© 2008 Microchip Technology Inc.  
DS39631E-page 253  
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