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PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
22.6 Operation During Sleep  
22.7 Effects of a Reset  
When enabled, the HLVD circuitry continues to operate  
during Sleep. If the device voltage crosses the trip  
point, the HLVDIF bit will be set and the device will  
wake-up from Sleep. Device execution will continue  
from the interrupt vector address if interrupts have  
been globally enabled.  
A device Reset forces all registers to their Reset state.  
This forces the HLVD module to be turned off.  
TABLE 22-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE  
Reset  
Values  
on Page  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
HLVDCON VDIRMAG  
IRVST  
HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0  
50  
49  
52  
52  
52  
INTCON  
PIR2  
GIE/GIEH PEIE/GIEL TMR0IE  
INT0IE  
EEIF  
RBIE  
BCLIF  
BCLIE  
BCLIP  
TMR0IF  
HLVDIF  
INT0IF  
RBIF  
OSCFIF  
OCSFIE  
OSCFIP  
CMIF  
CMIE  
CMIP  
TMR3IF CCP2IF  
PIE2  
EEIE  
EEIP  
HLVDIE TMR3IE CCP2IE  
HLVDIP TMR3IP CCP2IP  
IPR2  
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.  
© 2008 Microchip Technology Inc.  
Advance Information  
DS39631E-page 247