PIC18F2420/2520/4420/4520
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
20.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
±100 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
=
Input Capacitance
Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
CMCON
CVRCON
INTCON
PIR2
C2OUT
CVREN
C1OUT
CVROE
C2INV
CVRR
C1INV
CVRSS
INT0IE
EEIF
CIS
CM2
CM1
CVR1
INT0IF
CM0
CVR0
RBIF
51
51
52
52
52
52
52
52
52
CVR3
RBIE
BCLIF
BCLIE
BCLIP
RA3
CVR2
GIE/GIEH PEIE/GIEL TMR0IE
TMR0IF
HLVDIF
OSCFIF
OSCFIE
OSCFIP
RA7(1)
CMIF
CMIE
CMIP
RA6(1)
—
—
TMR3IF CCP2IF
PIE2
EEIE
HLVDIE TMR3IE CCP2IE
HLVDIP TMR3IP CCP2IP
IPR2
—
EEIP
PORTA
LATA
RA5
RA4
RA2
RA1
RA0
LATA7(1)
LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch)
TRISA
TRISA7(1) TRISA6(1) PORTA Data Direction Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various
primary oscillator modes. When disabled, these bits are read as ‘0’.
© 2008 Microchip Technology Inc.
DS39631E-page 237
MICROCHIP [ MICROCHIP ]
