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PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
and automatic shutdown and restart. The enhanced  
features are discussed in detail in Section 16.4  
“Enhanced PWM Mode”. Capture, Compare and  
single output PWM functions of the ECCP module are  
the same as described for the standard CCP module.  
16.0 ENHANCED CAPTURE/  
COMPARE/PWM (ECCP)  
MODULE  
Note:  
The ECCP module is implemented only in  
40/44-pin devices.  
The control register for the Enhanced CCP module is  
shown in Register 16-2. It differs from the CCPxCON  
registers in PIC18F2420/2520 devices in that the two  
Most Significant bits are implemented to control PWM  
functionality.  
In PIC18F4420/4520 devices, CCP1 is implemented as  
standard CCP module with Enhanced PWM  
a
capabilities. These include the provision for 2 or 4 output  
channels, user-selectable polarity, dead-band control  
REGISTER 16-1: CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES)  
R/W-0  
P1M1  
R/W-0  
P1M0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
DC1B1  
DC1B0  
CCP1M3  
CCP1M2  
CCP1M1  
CCP1M0  
bit 7  
bit 0  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
-n = Value at POR  
bit 7-6  
P1M<1:0>: Enhanced PWM Output Configuration bits  
If CCP1M3:CCP1M2 = 00, 01, 10:  
xx= P1A assigned as capture/compare input/output; P1B, P1C, P1D assigned as port pins  
If CCP1M3:CCP1M2 = 11:  
00= Single output, P1A modulated; P1B, P1C, P1D assigned as port pins  
01= Full-bridge output forward, P1D modulated; P1A active; P1B, P1C inactive  
10= Half-bridge output, P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins  
11= Full-bridge output reverse, P1B modulated; P1C active; P1A, P1D inactive  
bit 5-4  
DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0  
Capture mode:  
Unused.  
Compare mode:  
Unused.  
PWM mode:  
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in  
CCPR1L.  
bit 3-0  
CCP1M<3:0>: Enhanced CCP Mode Select bits  
0000= Capture/Compare/PWM off (resets ECCP module)  
0001= Reserved  
0010= Compare mode, toggle output on match  
0011= Capture mode  
0100= Capture mode, every falling edge  
0101= Capture mode, every rising edge  
0110= Capture mode, every 4th rising edge  
0111= Capture mode, every 16th rising edge  
1000= Compare mode, initialize CCP1 pin low; set output on compare match (set CCP1IF)  
1001= Compare mode, initialize CCP1 pin high; clear output on compare match (set CCP1IF)  
1010= Compare mode, generate software interrupt only; CCP1 pin reverts to I/O state  
1011= Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CCP1IF bit)  
1100= PWM mode, P1A, P1C active-high; P1B, P1D active-high  
1101= PWM mode, P1A, P1C active-high; P1B, P1D active-low  
1110= PWM mode, P1A, P1C active-low; P1B, P1D active-high  
1111= PWM mode, P1A, P1C active-low; P1B, P1D active-low  
© 2008 Microchip Technology Inc.  
DS39631E-page 147  
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