PIC18F2420/2520/4420/4520
FIGURE 10-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RE0
52
52
52
52
52
52
49
52
52
52
51
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Register
TRISD
PORTE
LATE
—
—
—
—
—
—
—
—
RE3
—
RE2
RE1
LATE Data Latch Register
TRISE
INTCON
PIR1
IBF
OBF
IBOV
PSPMODE
INT0IE
TXIF
—
TRISE2
TMR0IF
CCP1IF
TRISE1
INT0IF
TRISE0
RBIF
GIE/GIEH PEIE/GIEL TMR0IF
RBIE
SSPIF
SSPIE
SSPIP
PCFG3
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
TMR2IF
TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
RCIP
TXIP
ADCON1
VCFG1
VCFG0
PCFG2
PCFG1
PCFG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
© 2008 Microchip Technology Inc.
DS39631E-page 121
MICROCHIP [ MICROCHIP ]
