PIC18F2420/2520/4420/4520
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
52
52
52
51
51
51
LATA
LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch)
TRISA7(1) TRISA6(1) PORTA Data Direction Register
TRISA
ADCON1
CMCON
CVRCON
—
—
VCFG1
C2INV
CVRR
VCFG0
C1INV
PCFG3
CIS
PCFG2
CM2
PCFG1
CM1
PCFG0
CM0
C2OUT
CVREN
C1OUT
CVROE
CVRSS
CVR3
CVR2
CVR1
CVR0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
© 2008 Microchip Technology Inc.
DS39631E-page 107
MICROCHIP [ MICROCHIP ]
