PIC18F2420/2520/4420/4520
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
The Data Latch (LATA) register is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in the Configuration register (see
Section 23.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Data Latch register)
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the com-
parator voltage reference output. The operation of pins
RA<3:0> and RA5 as A/D Converter inputs is selected
by clearing or setting the control bits in the ADCON1
register (A/D Control Register 1).
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
Pins RA0 through RA5 may also be used as comparator
inputs or outputs by setting the appropriate bits in the
CMCON register. To use RA<3:0> as digital inputs, it is
also necessary to turn off the comparators.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
RD LAT
Note:
On a Power-on Reset, RA5 and RA<3:0>
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
Data
Bus
D
Q
I/O pin(1)
WR LAT
or
The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Port
CK
Data Latch
D
Q
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
EXAMPLE 10-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
07h
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
Q
D
CLRF
EN
EN
RD Port
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
07h
CMCON
0CFh
Note 1: I/O pins have diode protection to VDD and VSS.
; Configure comparators
; for digital input
; Value used to
10.1 PORTA, TRISA and LATA Registers
; initialize data
; direction
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
© 2008 Microchip Technology Inc.
DS39631E-page 105
MICROCHIP [ MICROCHIP ]
