PIC18F2480/2580/4480/4580
24.2.3.2
Message Acceptance Filters
and Masks
This section describes the message acceptance filters
and masks for the CAN receive buffers.
REGISTER 24-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER
REGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID<10:3>: Standard Identifier Filter bits (if EXIDEN = 0)
Extended Identifier Filter bits, EID<28:21> (if EXIDEN = 1).
Note 1: Registers, RXF6SIDH:RXF15SIDH, are available in Mode 1 and 2 only.
REGISTER 24-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER
REGISTERS, LOW BYTE [0 ≤ n ≤ 15](1)
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDEN(2)
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
SID<2:0>: Standard Identifier Filter bits (if EXIDEN = 0)
Extended Identifier Filter bits, EID<20:18> (if EXIDEN = 1).
Unimplemented: Read as ‘0’
bit 4
bit 3
EXIDEN: Extended Identifier Filter Enable bit(2)
1= Filter will only accept extended ID messages
0= Filter will only accept standard ID messages
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier Filter bits
Note 1: Registers, RXF6SIDL:RXF15SIDL, are available in Mode 1 and 2 only.
2: In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value.
DS39637D-page 308
© 2009 Microchip Technology Inc.
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