PIC18F2480/2580/4480/4580
REGISTER 24-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE
[0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0](1)
U-0
—
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
RXRTR: Receiver Remote Transmission Request bit
1= This is a remote transmission request
0= This is not a remote transmission request
bit 5
RB1: Reserved bit 1
Reserved by CAN Spec and read as ‘0’.
RB0: Reserved bit 0
bit 4
Reserved by CAN Spec and read as ‘0’.
DLC<3:0>: Data Length Code bits
bit 3-0
1111= Reserved
1110= Reserved
1101= Reserved
1100= Reserved
1011= Reserved
1010= Reserved
1001= Reserved
1000= Data length = 8 bytes
0111= Data length = 7 bytes
0110= Data length = 6 bytes
0101= Data length = 5 bytes
0100= Data length = 4 bytes
0011= Data length = 3 bytes
0010= Data length = 2 bytes
0001= Data length = 1 bytes
0000= Data length = 0 bytes
Note 1: These registers are available in Mode 1 and 2 only.
DS39637D-page 306
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
