PIC18F2480/2580/4480/4580
REGISTER 24-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 1]
U-0
—
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
RXRTR: Receiver Remote Transmission Request bit
1= Remote transfer request
0= No remote transfer request
bit 5
RB1: Reserved bit 1
Reserved by CAN Spec and read as ‘0’.
RB0: Reserved bit 0
bit 4
Reserved by CAN Spec and read as ‘0’.
DLC<3:0>: Data Length Code bits
bit 3-0
1111= Invalid
1110= Invalid
1101= Invalid
1100= Invalid
1011= Invalid
1010= Invalid
1001= Invalid
1000= Data length = 8 bytes
0111= Data length = 7 bytes
0110= Data length = 6 bytes
0101= Data length = 5 bytes
0100= Data length = 4 bytes
0011= Data length = 3 bytes
0010= Data length = 2 bytes
0001= Data length = 1 bytes
0000= Data length = 0 bytes
REGISTER 24-20: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS
[0 ≤ n ≤ 1, 0 ≤ m ≤ 7]
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RXBnDm7
RXBnDm6
RXBnDm5
RXBnDm4 RXBnDm3
RXBnDm2
RXBnDm1
RXBnDm0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-0
RXBnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0
to RXB0D7.
DS39637D-page 298
© 2009 Microchip Technology Inc.
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