PIC18F2480/2580/4480/4580
REGISTER 24-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED)
bit 2
bit 1
bit 0
Mode 0:
RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit
1= Receive Buffer 0 overflow will write to Receive Buffer 1
0= No Receive Buffer 0 overflow to Receive Buffer 1
Mode 1, 2:
FILHIT2: Filter Hit bit 2
This bit combines with other bits to form filter acceptance bits<4:0>.
Mode 0:
JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)(2)
1= Allows jump table offset between 6 and 7
0= Allows jump table offset between 1 and 0
Mode 1, 2:
FILHIT1: Filter Hit bit 1
This bit combines with other bits to form filter acceptance bits<4:0>.
Mode 0:
FILHIT0: Filter Hit bit 0
This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0.
1= Acceptance Filter 1 (RXF1)
0= Acceptance Filter 0 (RXF0)
Mode 1, 2:
FILHIT0: Filter Hit bit 0
This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the message reception
into this receive buffer.
01111= Acceptance Filter 15 (RXF15)
01110= Acceptance Filter 14 (RXF14)
...
00000= Acceptance Filter 0 (RXF0)
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the
buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full.
After clearing the RXFUL flag, the PIR3 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is
not cleared, then RXB0IF is set again.
2: This bit allows same filter jump table for both RXB0CON and RXB1CON.
DS39637D-page 294
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
