PIC18F2480/2580/4480/4580
8.6
Operation During Code-Protect
8.8
Using the Data EEPROM
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specification D124. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 25.0
“Special Features of the CPU” for additional
information.
8.7
Protection Against Spurious Write
A simple data EEPROM refresh routine is shown in
Example 8-3.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33).
Note:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
EXAMPLE 8-3:
DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF
EEADR
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
LOOP
BSF
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
EEADR, F
LOOP
; Increment address
; Not zero, do it again
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
DS39637D-page 114
© 2009 Microchip Technology Inc.
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