PIC18F2480/2580/4480/4580
EXAMPLE 7-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1,EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start program (CPU stall)
DECFSZ COUNTER1
BRA
BSF
BCF
WRITE_BUFFER_BACK
INTCON, GIE
EECON1, WREN
; re-enable interrupts
; disable write to memory
7.5.2
WRITE VERIFY
7.5.4
PROTECTION AGAINST SPURIOUS
WRITES
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 25.0 “Special Features of the
CPU” for more detail.
7.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
7.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
See Section 25.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 7-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
TBLPTRU
—
—
bit21(3) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
55
55
55
55
55
57
57
57
58
58
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INTE
RBIE
TMR0IF
INTF
WR
RBIF
RD
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1
IPR2
EEPGD
CFGS
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR
BCLIP
BCLIF
BCLIE
WREN
HLVDIP
HLVDIF
HLVDIE
OSCFIP CMIP(2)
OSCFIF CMIF(2)
OSCFIE CMIE(2)
TMR3IP ECCP1IP(1)
TMR3IF ECCP1IF(1)
TMR3IE ECCP1IE(1)
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: These bits are available in PIC18F4X80 devices only.
2: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices.
3: This bit is available only in Test mode and Serial Programming mode.
© 2009 Microchip Technology Inc.
DS39637D-page 109
MICROCHIP [ MICROCHIP ]
