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PIC18F4520-I/PT 参数 Datasheet PDF下载

PIC18F4520-I/PT图片预览
型号: PIC18F4520-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
EXAMPLE 6-3:  
WRITING TO FLASH PROGRAM MEMORY  
MOVLW  
D'64  
; number of bytes in erase block  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
COUNTER  
BUFFER_ADDR_HIGH  
FSR0H  
BUFFER_ADDR_LOW  
FSR0L  
CODE_ADDR_UPPER  
TBLPTRU  
CODE_ADDR_HIGH  
TBLPTRH  
CODE_ADDR_LOW  
TBLPTRL  
; point to buffer  
; Load TBLPTR with the base  
; address of the memory block  
READ_BLOCK  
TBLRD*+  
MOVF  
MOVWF  
; read into TABLAT, and inc  
; get data  
; store data  
; done?  
TABLAT, W  
POSTINC0  
DECFSZ COUNTER  
BRA  
READ_BLOCK  
; repeat  
MODIFY_WORD  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
DATA_ADDR_HIGH  
FSR0H  
DATA_ADDR_LOW  
FSR0L  
NEW_DATA_LOW  
POSTINC0  
NEW_DATA_HIGH  
INDF0  
; point to buffer  
; update buffer word  
ERASE_BLOCK  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BSF  
BCF  
BSF  
BSF  
BCF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BSF  
CODE_ADDR_UPPER  
TBLPTRU  
CODE_ADDR_HIGH  
TBLPTRH  
CODE_ADDR_LOW  
TBLPTRL  
EECON1, EEPGD  
EECON1, CFGS  
EECON1, WREN  
EECON1, FREE  
INTCON, GIE  
55h  
EECON2  
0AAh  
EECON2  
EECON1, WR  
INTCON, GIE  
; load TBLPTR with the base  
; address of the memory block  
; point to Flash program memory  
; access Flash program memory  
; enable write to memory  
; enable Row Erase operation  
; disable interrupts  
Required  
Sequence  
; write 55h  
; write 0AAh  
; start erase (CPU stall)  
; re-enable interrupts  
; dummy read decrement  
; point to buffer  
BSF  
TBLRD*-  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BUFFER_ADDR_HIGH  
FSR0H  
BUFFER_ADDR_LOW  
FSR0L  
WRITE_BUFFER_BACK  
MOVLW  
D’32  
; number of bytes in holding register  
MOVWF  
WRITE_BYTE_TO_HREGS  
MOVFF  
COUNTER  
POSTINC0, WREG  
TABLAT  
; get low byte of buffer data  
; present data to table latch  
; write data, perform a short write  
; to internal TBLWT holding register.  
; loop until buffers are full  
MOVWF  
TBLWT+*  
DECFSZ COUNTER  
BRA WRITE_WORD_TO_HREGS  
DS39631E-page 80  
© 2008 Microchip Technology Inc.  
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