PIC18F2420/2520/4420/4520
4.0
RESET
The PIC18F2420/2520/4420/4520 devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET
Instruction
Stack Full Reset
Stack Underflow Reset
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
BOR is covered in
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
WDT Resets are covered in
FIGURE 4-1:
RESET
Instruction
Stack
Pointer
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset
MCLR
MCLRE
( )_IDLE
Sleep
WDT
Time-out
V
DD
Rise
Detect
V
DD
Brown-out
Reset
BOREN
OST/PWRT
OST
OSC1
32
μs
INTRC
(1)
1024 Cycles
R
Q
10-Bit Ripple Counter
Chip_Reset
S
POR Pulse
PWRT
65.5 ms
11-Bit Ripple Counter
Enable PWRT
Enable OST
(2)
Note 1:
2:
This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
See Table 4-2 for time-out situations.
©
2008 Microchip Technology Inc.
DS39631E-page 41
MICROCHIP [ MICROCHIP TECHNOLOGY ]
