PIC18F2420/2520/4420/4520
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA
n
Syntax:
BSF f, b {,a}
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
(PC) + 2 + 2n → PC
Status Affected: None
Operation:
1→ f<b>
Encoding:
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Description:
Add the 2’s complement number, ‘2n’, to
the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
HERE
BRA Jump
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
© 2008 Microchip Technology Inc.
DS39631E-page 279
MICROCHIP [ MICROCHIP ]
