PIC18F2420/2520/4420/4520
23.0
SPECIAL FEATURES OF
THE CPU
PIC18F2420/2520/4420/4520 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components. These
are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2420/2520/4420/
4520 devices have a Watchdog Timer, which is either
permanently enabled via the Configuration bits or
software controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
23.1
Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location, 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a
TBLWT
instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a
TBLWT
instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to
TABLE 23-1:
File Name
300001h
300002h
300003h
300005h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFFh
Legend:
Note 1:
2:
CONFIGURATION BITS AND DEVICE IDs
Bit 7
IESO
—
—
DEBUG
—
CPD
—
WRTD
—
—
DEV2
DEV10
Bit 6
FCMEN
—
—
—
XINST
—
CPB
—
WRTB
—
EBTRB
DEV1
DEV9
Bit 5
—
—
—
—
—
—
—
—
WRTC
—
—
DEV0
DEV8
Bit 4
—
BORV1
WDTPS3
—
—
—
—
—
—
—
—
REV4
DEV7
Bit 3
FOSC3
BORV0
WDTPS2
—
—
CP3
—
WRT3
—
EBTR3
(1)
—
REV3
DEV6
(1)
(1)
Bit 2
FOSC2
BOREN1
Bit 1
FOSC1
Bit 0
FOSC0
WDTEN
CCP2MX
STVREN
CP0
—
WRT0
—
EBTR0
—
REV0
DEV3
Default/
Unprogrammed
Value
00-- 0111
---1 1111
---1 1111
1--- -011
10-- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
xxxx xxxx
(2)
xxxx xxxx
(2)
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
DEVID2
BOREN0 PWRTEN
WDTPS1 WDTPS0
LPT1OSC PBADEN
LVP
CP2
—
WRT2
—
EBTR2
(1)
—
REV2
DEV5
(1)
(1)
CONFIG3H MCLRE
—
CP1
—
WRT1
—
EBTR1
—
REV1
DEV4
3FFFFEh DEVID1
x
= unknown,
u
= unchanged, — = unimplemented,
q
= value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Unimplemented in PIC18F2420/4420 devices; maintain this bit set.
See Register 23-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
©
2008 Microchip Technology Inc.
DS39631E-page 249
MICROCHIP [ MICROCHIP TECHNOLOGY ]
