PIC18F2420/2520/4420/4520
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
52
52
52
49
49
49
51
LATB
PORTB Data Latch Register (Read and Write to Data Latch)
PORTB Data Direction Register
TRISB
INTCON
INTCON2
INTCON3
ADCON1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
RBPU
INT2IP
—
INTEDG0 INTEDG1 INTEDG2
INT1IP
—
—
INT2IE
VCFG0
INT1IE
PCFG3
INT2IF
PCFG1
INT1IF
PCFG0
VCFG1
PCFG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
DS39631E-page 110
© 2008 Microchip Technology Inc.