PIC18F2420/2520/4420/4520
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
4.6
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations, as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
RCON Register
STKPTR Register
Program
Counter
Condition
RI
TO
PD
POR BOR STKFUL
STKUNF
Power-on Reset
RESETInstruction
Brown-out Reset
0000h
0000h
0000h
0000h
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
MCLR Reset during Power-Managed
Run Modes
MCLR Reset during Power-Managed
Idle Modes and Sleep Mode
0000h
0000h
0000h
u
u
u
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
WDT Time-out during Full Power or
Power-Managed Run Mode
MCLR Reset during Full-Power
Execution
Stack Full Reset (STVREN = 1)
0000h
0000h
0000h
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
1
u
u
u
1
1
Stack Underflow Reset (STVREN = 1)
Stack Underflow Error (not an actual
Reset, STVREN = 0)
WDT Time-out during
Power-Managed Idle or Sleep Modes
PC + 2
u
u
0
u
0
0
u
u
u
u
u
u
u
u
Interrupt Exit from Power-Managed
Modes
PC + 2(1)
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
DS39631E-page 48
© 2008 Microchip Technology Inc.
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