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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
advantageous to use the high baud rate (BRGH = 1) or  
the 16-bit BRG to reduce the baud rate error, or  
18.1  
Baud Rate Generator (BRG)  
The BRG is a dedicated, 8-bit or 16-bit generator that  
supports both the Asynchronous and Synchronous  
modes of the EUSART. By default, the BRG operates  
in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)  
selects 16-bit mode.  
achieve a slow baud rate for a fast oscillator frequency.  
Writing a new value to the SPBRGH:SPBRG registers  
causes the BRG timer to be reset (or cleared). This  
ensures the BRG does not wait for a timer overflow  
before outputting the new baud rate.  
The SPBRGH:SPBRG register pair controls the period  
of a free-running timer. In Asynchronous mode, bits,  
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>), also  
control the baud rate. In Synchronous mode, BRGH is  
ignored. Table 18-1 shows the formula for computation  
of the baud rate for different EUSART modes which  
only apply in Master mode (internally generated clock).  
18.1.1  
OPERATION IN POWER-MANAGED  
MODES  
The device clock is used to generate the desired baud  
rate. When one of the power-managed modes is  
entered, the new clock source may be operating at a  
different frequency. This may require an adjustment to  
the value in the SPBRG register pair.  
Given the desired baud rate and FOSC, the nearest  
integer value for the SPBRGH:SPBRG registers can be  
calculated using the formulas in Table 18-1. From this,  
the error in baud rate can be determined. An example  
calculation is shown in Example 18-1. Typical baud  
rates and error values for the various Asynchronous  
modes are shown in Table 18-2. It may be  
18.1.2  
SAMPLING  
The data on the RX pin is sampled three times by a  
majority detect circuit to determine if a high or a low  
level is present at the RX pin.  
TABLE 18-1: BAUD RATE FORMULAS  
Configuration Bits  
BRG/EUSART Mode  
Baud Rate Formula  
SYNC  
BRG16  
BRGH  
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-Bit/Asynchronous  
8-Bit/Asynchronous  
16-Bit/Asynchronous  
16-Bit/Asynchronous  
8-Bit/Synchronous  
16-Bit/Synchronous  
FOSC/[64 (n + 1)]  
FOSC/[16 (n + 1)]  
FOSC/[4 (n + 1)]  
Legend: x= Don’t care, n = value of SPBRGH:SPBRG register pair  
© 2008 Microchip Technology Inc.  
DS39631E-page 205  
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