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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
FIGURE 17-27:  
BUS COLLISION DURING START CONDITION (SCL = 0)  
SDA = 0, SCL = 1  
TBRG  
TBRG  
SDA  
Set SEN, enable Start  
sequence if SDA = 1, SCL = 1  
SCL  
SEN  
SCL = 0before SDA = 0,  
bus collision occurs. Set BCLIF.  
SCL = 0before BRG time-out,  
bus collision occurs. Set BCLIF.  
BCLIF  
Interrupt cleared  
in software  
S
0’  
0’  
0’  
0’  
SSPIF  
FIGURE 17-28:  
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION  
SDA = 0, SCL = 1  
Set S  
Set SSPIF  
Less than TBRG  
TBRG  
SDA pulled low by other master.  
Reset BRG and assert SDA.  
SDA  
SCL  
S
SCL pulled low after BRG  
time-out  
SEN  
Set SEN, enable Start  
sequence if SDA = 1, SCL = 1  
0’  
BCLIF  
S
SSPIF  
Interrupts cleared  
in software  
SDA = 0, SCL = 1,  
set SSPIF  
© 2008 Microchip Technology Inc.  
DS39631E-page 197  
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