PIC18F45J10 FAMILY
FIGURE 1-2:
PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
21
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
RA5/AN4/SS1/C2OUT
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
31 Level Stack
STKPTR
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
RB2/INT2/AN8
Program Memory
(16/32 Kbytes)
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
12
Data Latch
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
8
Table Latch
PORTC
Address
Decode
ROM Latch
IR
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
Instruction Bus <16>
RC3/SCK1/SCL1
RC4/SDI1/SDA1
RC5/SDO1
8
RC6/TX/CK
State Machine
Control Signals
Instruction
Decode and
Control
RC7/RX/DT
PRODH PRODL
8 x 8 Multiply
PORTD
3
RD0/PSP0/SCK2/SCL2
RD1/PSP1/SDI2/SDA2
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
8
W
BITOP
8
8
8
VDDCORE
OSC1
Internal
Oscillator
Block
Power-up
Timer
8
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
OSC2
T1OSI
T1OSO
Power-on
Reset
Watchdog
Timer
Brown-out(2)
Reset
Fail-Safe
PORTE
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
Precision
Band Gap
Reference
Single-Supply
Programming
In-Circuit
MCLR
VDD, VSS
Clock Monitor
Debugger
ADC
10-Bit
BOR(2)
Timer0
ECCP1
Timer1
CCP2
Timer2
MSSP
Comparator
EUSART
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
© 2009 Microchip Technology Inc.
DS39682E-page 11
MICROCHIP [ MICROCHIP ]
