PIC18F45J10 FAMILY
Transition for Wake From Idle to Run Mode .............. 39
Transition for Wake From Sleep ................................ 38
Transition From RC_RUN Mode to
V
Voltage Reference Specifications .................................... 316
Voltage Regulator (On-Chip) ........................................... 243
PRI_RUN Mode ................................................. 37
Transition to RC_RUN Mode ..................................... 37
Timing Diagrams and Specifications
W
Watchdog Timer (WDT) ........................................... 235, 242
Associated Registers ............................................... 242
Control Register ....................................................... 242
During Oscillator Failure .......................................... 245
Programming Considerations .................................. 242
WCOL ...................................................... 180, 181, 182, 185
WCOL Status Flag ................................... 180, 181, 182, 185
WWW Address ................................................................ 363
WWW, On-Line Support ...................................................... 6
A/D Conversion Requirements ................................ 335
AC Characteristics
Internal RC Accuracy ....................................... 320
Capture/Compare/PWM Requirements
(Including ECCP Module) ................................ 324
CLKO and I/O Requirements ................................... 321
EUSART Synchronous Receive
Requirements .................................................. 333
EUSART Synchronous Transmission
X
Requirements .................................................. 333
Example SPI Mode Requirements
XORLW ........................................................................... 289
XORWF ........................................................................... 290
(CKE = 0) ................................................. 325, 327
Example SPI Mode Requirements
(CKE = 1) ......................................................... 326
Example SPI Slave Mode Requirements (CKE = 1) 328
External Clock Requirements .................................. 319
2
I C Bus Data Requirements (Slave Mode) .............. 330
2
I C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 329
2
Master SSP I C Bus Data Requirements ................ 332
2
Master SSP I C Bus Start/Stop Bits
Requirements .................................................. 331
Parallel Slave Port Requirements ............................ 324
PLL Clock ................................................................. 320
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 322
Timer0 and Timer1 External Clock
Requirements .................................................. 323
Top-of-Stack Access .......................................................... 53
TRISE Register
PSPMODE Bit .......................................................... 107
TSTFSZ ........................................................................... 289
Two-Speed Start-up ................................................. 235, 244
Two-Word Instructions
Example Cases .......................................................... 57
TXSTA Register
BRGH Bit ................................................................. 197
© 2009 Microchip Technology Inc.
DS39682E-page 361
MICROCHIP [ MICROCHIP ]
