PIC18F45J10 FAMILY
3.6.1
OSCILLATOR CONTROL REGISTER
3.6.1.1
System Clock Selection and the
FOSC2 Configuration Bit
The OSCCON register (Register 3-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator defined by FOSC<1:0> (that is, one of the HC
or EC modes) is used as the primary clock source on
device Resets.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<2:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the internal oscillator. The clock source changes after
one or more of the bits are written to, following a brief
clock transition interval.
The default clock configuration on Reset can be changed
with the FOSC2 Configuration bit. The effect of this bit is
to set the clock source selected when SCS<1:0> = 00.
When FOSC2 = 1 (default), the oscillator source
defined by FOSC<1:0> is selected whenever
SCS<1:0> = 00. When FOSC2 = 0, the INTRC oscillator
is selected whenever SCS<1:0> = 00. Because the SCS
bits are cleared on Reset, the FOSC2 setting also
changes the default oscillator mode on Reset.
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in sec-
ondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits is set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It will serve as the
clock source until the device has loaded its configura-
tion values from memory. It is at this point that the
FOSC Configuration bits are read and the oscillator
selection of operational mode is made.
Note that either the primary clock or the internal
oscillator will have two bit setting options, at any given
time, depending on the setting of FOSC2.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
3.6.2
OSCILLATOR TRANSITIONS
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
PIC18F45J10 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEPinstruction will be ignored.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEPinstruction or a very
long delay may occur while the Timer1
oscillator starts.
© 2009 Microchip Technology Inc.
DS39682E-page 31
MICROCHIP [ MICROCHIP ]
